blog.dave.tf

UTL comes from FastLanes, and is designed to make delta decoding very data-parallel.

This is a slightly cleaned up version of something I felt compelled to write recently, for a different audience in a different context.

The Lattice ECP5 is a capable little FPGA, and has good support for open-source synthesis through the Yosys EDA toolchain.

The very short version of the clickbait title: if you create TAI64 timestamps and your implementation mimics libtai, then your timestamps are likely not TAI.

If you’ve never read the classic Reflections on Trusting Trust, and you like the idea of being unsettled about the foundations of computing, go have a read.

I recently got a ULX3S FPGA board, and have been playing with it.

In my quest to write a fast IPv4+6 parser, I wrote a slow-but-I-think-correct parser, to use as a base of comparison.

Recently I had a chat with the excellent Vallery Lancey, about Kubernetes.

In parts one, two and three, we went from requirements to a honking big Ebay order of various computer parts.

In parts one and two we went from a list of requirements to a set of constraints on the hardware we’ll need to buy.

In part one we got together some requirements, and got a rough idea of the kind of server we’re thinking about.

A friend would like a new NAS, with a combo of features and performance that would normally place them in the $10k+ range for enterprise grade storage.

As I was setting up my new NAS, I got a nasty surprise: psrinfo, Illumos’s command to list processor information, told me that my CPU only has 1 core.

In a marathon of Bryan Cantrill interviews, Bryan wondered out loud why “jumbo” ethernet frames are 9000 bytes.