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Articole: 4
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TL;DR: I have spent the last few months learning about and implementing a 2:4 bfloat16 Sparse GEMM kernel in CUDA.
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Memory coalescing occurs when all threads in a warp access a contiguous chunk of data from global memory.
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TL;DR: I develop a IO-aware kernel for the RG-LRU in Triton.
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TL;DR I improve upon my earlier codebase by implementing ZeRO-1 optimizer sharding using a combination of xmap and pjit.