A blog about a computer made from relays on Relay Computer

Talk about raking over old coals!

Well, it’s only taken 12 years but my computer has finally reached a major milestone - Turing completeness.

For a while now my computer has been missing its final three instruction classes … and two of them are ‘up there’ alongside branching in terms of overall importance for the capability of my relay computer.

Way back in 2019 I discussed how you can’t ‘half design a PCB’ and that, as a result, my controller cards already have all the required functionality laid down … I just haven’t explained how those ‘missing’ bits of functionality work in this blog yet.

In the last episode of this mini-series I explained about how an assembler’s job is effectively to convert a program written in a language a human programmer can understand (assembly language in this case) into something which a computer can understand.

Well, what a journey that’s been then … I started work on a clock for my relay computer back in May 2020 and today (20th Nov 2022) this post marks the end of it.

Quite a while ago I decided to give up on the tedious wire wrap technique for building my cards.

To make my relay computer do something interesting (or anything at all) it needs a list of instructions held in memory.

So, is fair to say that things have been a bit quiet around here of late … and if you’ve been following my YouTube channel I do hope you haven’t been holding your breath for the next episode of ‘making a relay computer clock’ as the last episode came out…

As the clock struck midnight at the very end of 2019 I decided, over a glass of something sparkling, that I’d set myself a challenge to put out a series of six YouTube videos within the space of one month.

In my last post I covered off the full design for the decoder card so all that remains is to get it soldered up and tested.

I’ve almost got everything I need now to get my relay computer to do branching.

In my last couple of posts I covered off the full design for the controller unit.

In my last couple of posts I finalised the controller schematic designs for the ALU, SETAB, MOV8 and GOTO class of instructions.

In my last post I covered off the controller design for the GOTO instruction.

With the sequencer now designed and constructed I’m much closer to getting branching working on my relay computer.

In my last couple of posts I covered off the full design for the sequencer unit.

I’ve got the designs for the 24-cycle FSM and pulse distribution in place so all that’s left for the sequencer is to bring the schematics together and then design the PCBs … and yup, that’s PCBs plural as this is going to be another part of the computer t…

In my last post I extended the 8-cycle FSM (finite state machine) design all the way up to 24-cycles so that we can run longer and more complicated instructions.

Recently I’ve been looking at what’s needed to implement branching in my computer (the upcoming GOTO class of instructions).

In my last post I covered the design for the GOTO opcode which will enable my relay computer to perform branching, loops and so on.

There’s been a common theme recently in the comments on my YouTube videos … people are ready to see my relay computer gain the power of branching and become a ‘proper’ computer … and that’s fair enough because that’s the point where the computer can do way

It’s time for the oddly therapeutic part of designing a PCB … laying out the board.

In my last couple of posts I’ve been building up to a change of approach in how I’m making the cards in my computer.

After years of using pad/prototyping boards to build my computer I’ve decided to switch things up a bit and have a go at making a custom PCB.

In my last post I touched on how the repetitive nature of making register cards has been putting me off progressing my relay computer.

… or so the proverb goes … and it’s fair to say I’ve been procrastinating quite a bit recently.

In my last three posts I covered the design of the auxiliary control unit which will ease entering and inspecting programs in the computer’s memory.

This is the last post in a mini-series of three covering the design of the auxiliary control unit which will ease entering and inspecting programs in the computer’s memory.

In my last post I made a start on the auxiliary control design which once completed will make it much easier to load instructions in to memory - effectively it’s a computer within a computer.

My relay computer is now at the point where it can execute a program in memory without assistance.

This is a bit of a landmark moment … at least for the construction of my relay computer.

In my last two posts I covered the construction of the upper and lower incrementer cards.

In my last post I covered the construction of the lower incrementer card which is effectively a 16-bit half adder.

We’re getting nearer and nearer to a computer that can run though a program in memory rather than just a single instruction … we’ve got memory to hold the program and a program counter to point to the current instruction in memory.

I’ve covered the construction of the upper and lower memory cards in my last two posts … it’s now time to bring those two cards together to form the memory unit proper and give it all a test.

In my last post I made a start on the memory unit construction with the lower memory card.

It’s time to make a start on the construction of the memory unit and as mentioned in my last post this one is a bit more complex than ‘boring old registers’ and so I’ll split it over two posts.

In my last couple of posts I’ve been slightly distracted by some ‘miscellany’ but now I return to form and crack on with constructing the program counter.

Continuing on with the theme from my last post … here is another ‘miscellany special’ covering all the little ‘side jobs’ I’ve been doing on my relay computer alongside the primary work of constructing the Program Counter, Memory and Incrementer cards.

Having somehow forgotten to take time off work I’m now playing ‘annual leave catch up’ which means lots of four day weeks but also, and more importantly for this blog, I’m getting time to crack on with construction of my relay computer.

The design of the computer’s memory, incrementer and program counter are now complete but there’s one last piece of the ‘puzzle’ required to get the computer running a program.

In my last post I started the design for the computer’s memory unit which is spread over two cards.

In my last post I explained my decision to use a ‘modern’ memory chip in my relay computer … I also alluded to there being some complexities in interfacing the rest of the computer with that memory chip.

It’s time, at last, to start looking at the design for the computer’s memory and this is a bit of a game changer as it’s the final part of the jigsaw that lets the computer run a program.

I’ve nearly got the design for the memory cards done and ready to share but once that’s out the way it’ll be time to get on with some construction again.

In my last post I covered the design of the 16-bit half adder which takes whatever value is currently on the address bus and increments it by one.

In the last post I introduced the design for the 1-bit Half Adder.

Typical isn’t it?!

It’s been a while since my last post … pretty much 10 months in fact … and I’d love to say I’ve been quietly working on my relay computer in the meantime but I haven’t.