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Articole: 19

  1. Pushing UberDDR3 Frequency Through RTL Cleanup - Post #18

    (OpenIPHub)

    A step-by-step walkthrough of pushing UberDDR3 from 90 MHz to 132 MHz using RTL cleanup and the OpenXC7 open-source FPGA flow.

  2. FPGA Builds Without Local Toolchains: An Intro to CaaS - Post #17

    (OpenIPHub)

    If you’ve been curious about open-source FPGA flows but felt blocked by setup complexity, CaaS makes it simple for you,

  3. How UberDDR3 Stays Stable: GoCD-Powered CI for Serious Hardware - Post #16

    (OpenIPHub)

    Read through how UberDDR3 uses GoCD for its CI pipeline: from lint to full hardware build!

  4. UberDDR3 on Lattice ECP5: Expanding FPGA Support - Post #15

    (OpenIPHub)

    UberDDR3 now running on Lattice ECP5!

  5. UberDDR3 + OpenXC7: Open-Source DDR3 Controller Meets Open-Source FPGA Toolchain - Post #14

    (OpenIPHub)

    UberDDR3, the open-source DDR3 controller, now works with OpenXC7, the open-source FPGA toolchain!

  6. Pushing UberDDR3 to Higher Speeds: DDR3-1333 & DDR3-1600! - Post #13

    (OpenIPHub)

    UberDDR3 has come a long way!

  7. Thermal Management for UberDDR3 with XADC - Post #12

    (OpenIPHub)

    Explore how to integrate XADC with UberDDR3 for thermal management

  8. SPD Reader for UberDDR3 - Post #11

    (OpenIPHub)

    Serial Presence Detect (SPD) reader for UberDDR3

  9. Unlocking More Memory: Dual-Rank DIMM Support in UberDDR3 - Post #10

    (OpenIPHub)

    Dual rank support is now available!

  10. UberDDR3 Self-Refresh: Reducing Power Consumption in Idle Periods - Post #9

    (OpenIPHub)

    Elaborates on the new self-refresh feature, with testbench simulation and project demonstration

  11. UberDDR3 + MicroBlaze (Part 2) - Post #8

    (OpenIPHub)

    Implement Dhrystone Test and Ethernet Echo Server powered by UberDDR3!

  12. UberDDR3 + MicroBlaze (Part 1) - Post #7

    (OpenIPHub)

    Learn how to add UberDDR3 into the Vivado IP catalog and integrate with MicroBlaze Block Design.

  13. UberDDR3 Feature Update: Error Correction (Part 2) - Post #6

    (OpenIPHub)

    Explore the more advanced in-line ECC implementation on UberDDR3

  14. UberDDR3 Update: Error Correction (Part 1) - Post #5

    (OpenIPHub)

    UberDDR3 New Feature Alert: Error Correction Code is now available!

  15. UberDDR3 Update: AXI4 Interface - Post #4

    (OpenIPHub)

    UberDDR3 new feature alert: AMBA AXI4 interface is now available!

  16. Getting Started with UberDDR3 (Part 2) - Post #3

    (OpenIPHub)

    Tutorial on implementing UberDDR3 on actual hardware with an example design demonstration

  17. Getting Started with UberDDR3 (Part 1) - Post #2

    (OpenIPHub)

    Tutorial on how to run simulations in UberDDR3 and understand how it operates beneath the surface.

  18. UberDDR3: An Opensource DDR3 Controller - Post #1

    (OpenIPHub)

    Introduction to UberDDR3 Project, its current and upcoming features.

  19. Introducing OpenIPHub: Your Gateway to Digital IC Design and FPGA Projects - Post #0

    (OpenIPHub)

    Welcome to OpenIpHub a place where my journey with digital design and FPGA projects gets shared with you