Bits'n'Bites

In this article I will describe a technique that can often compress the chroma data of an image to less than 0.5 bits per pixel on average, without visible artifacts.

A long standing misconception that dates back to the RISC vs CISC debate of the 1980’s is that CISC ISA:s yield better machine code density than RISC ISA:s.

This is a quick introduction to software development for the MRISC32 architecture.

If you are like me and spend a lot of time looking at assembly language output from compilers, this article may not provide much new information.

According to Flynn’s taxonomy SIMD refers to a computer architecture that can process multiple data streams with a single instruction (i.e.

The MRISC32 instruction set architecture recently reached a seemingly insignificant but major milestone: As of version 0.2 of the ISA the key elements of the Base architecture have been fixed, and it is very unlikely that any changes will be made to it any

Here is a short report on the current state of my MC1 project, which is an SoC design for FPGA:s.

This time I want to talk about some future directions for the MRISC32 vector model.

I recently implemented support for conditional move (or more precisely, conditional select) for the MRISC32 ISA, and I wanted to share some thoughts on that.

I’ve been developing software for over 30 years, and during those years I have frequently come across problems relating to a few features of the IEEE 754 floating point standard, namely: Denormalized numbers Configurable rounding modes Recently I have also