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A port/iteration of refsw2 to FPGAs!

Can h.265 compress network parameters?

An in-browser emulator for the GreenArrays GA144 with a twist.

A public retrospective on the Reicast/Flycast and FEX-Emu/hex-emu dramas.

Multi-threaded, multi-process JIT object code cache for hex-emu with BST index and crash safety.

Thought experiment on running Dreamcast emulation on the PS2 hardware.

Ahead-of-time IR caching that cuts clang launch time from 1.3s to 0.38s under FEX-Emu.

First steps implementing the Dreamcast's CLX2 CORE rendering unit in HLS for FPGA.

An in-depth interview covering the history of NullDC and Reicast, the Dreamcast emulation scene, and the technical journey behind these projects.

Step-by-step guide to running Android apps on Raspberry Pi 4 via Anbox.

How fixing pointer aliasing, signed modulo, and using SSE/AVX intrinsics yielded a 32% speedup in reicast's TA processing.

A novel technique for handling endian conversion in emulators using negative memory offsets.

Redesigned the Reicast automated builds page with jquery, underscorejs and regex.

Streaming Dreamcast rendering over websockets using glReadPixels and WebGL.

First reicast test on NVIDIA Jetson TK1 - amazing Dreamcast emulation performance.

Add wait states for ICE & module integration on the CPU.

ICE state machine implementation, got it talking with the debugger - VGA writes working!

Get the modularised code back into working state.

Modularization and refactoring of the SoC codebase.

Work on the ICE implementation.

Worked around the IO/DCM issues.

Almost implemented UART.

Investigate serial communications, try out UART sample, draft out ICE spec.

No luck locating the VGA corruption bug - simulator results and simpler test cases work fine.

Fixed VGA, centered image - still outputs corrupted data though.

Implemented beq, bga, bgt, jr, draw, fixed write16/read16.

Debug, debug, debug, and simulate.

Implemented RAM and added delays for RAM.

Spec now has vsync, reviewed sdlcore code, hacked together some very basic Verilog.

Debugged and finished the sdlcore implementation.

Discuss and improve specs, update documentation and C# reference implementation.

Brainstorming the final CPU design, porting to Verilog, and assembler implementation, at hackerspace.gr.

ISA design - ALU, branching, registers, load/store.

Introduction to computer architecture - buses, ALU, registers, instruction sets.

Clocked vs asynchronous design, clock dividers, clock domains, buffers, FIFOs, and pipelines, at hackerspace.gr.

Xilinx tooling, VHDL & Verilog introduction - design goals, history, syntax, and hands-on basics, at hackerspace.gr.

Fast recap of digital electronics basics - binary system, logic gates, combinational and sequential circuits, at hackerspace.gr.

ndce compiles with psl1ght, but no 3D output yet.

ARM code-path ported to Android, dynamic code running on PS3.

Back to coding after a break - nullDCe on Android, PPC rec improvements for Wii.

nullDCe showing first visuals on PS3 - main menu and VMUs working.

Basic cross compile of nulldce core working on PS3, now targeting open toolchain.

Officially back to working on nullDC, with plans for PS3 and Xbox ports.

nullDC dynarec instrumentation and profiling results for Shenmue.

nullDC mainline code released as open source on Google Code.

New dynarec with IL, backends for x86/arm/mips-allegrex, and first PSP/BeagleBoard results.

Setting expectations about nullDC/psp development, speed, and future ports.

GDrom support added, DOA2LE and SOTB running on PSP.