Shane Colton

Earlier this year, I got to do some TinyCross ice racing on a frozen lake: Thanks to Dane for organizing the event; there were over a dozen crazy ice vehicles.

In its original design, TinyCross used four identical Alien Power System 6374 170rpm/V brushless motors.

In a half-bridge configuration, the power loop is the path from the DC bus capacitor positive terminal to the output switch node and back to the capacitor negative terminal.

It's been a while since I've attempted a new motor drive design, the last one being TinyCross's dual-motor 50V/100A drive about six years ago.

In Part 2, I described PCIe as a bi-directional memory bus extension and looked at some factors that contribute to the efficiency of the link.

The Link Training and Status State Machine (LTSSM) is a logic block that sits in the MAC layer of the PCIe stack.

This post continues an exploration into the inner workings of PCIe.

Before getting too caught up in the inner workings of PCIe, it's probably worth taking a look at the high-level architecture - how it's used in a system and what the PCIe controller stack looks like.

Over the past few years, I've been developing and improving very fast standalone NVMe-based storage capability for the Zynq Ultrascale+ architecture, to keep up with the absurd speeds of modern SSDs.

This is a quick follow-up to my original post on speed testing bare metal NVMe with the Zynq Ultrascale+ AXI-PCIe bridge.

In the last post, I finally did some actual data logging with TinyCross set up in 4WD, 80A peak per motor, which is the rated current.

It's been a long time since I did a proper test drive with TinyCross, although I've taken it out just for fun a few times.

It's summer, which means it's time to work on go-karts.

Now that I've got a continuous multi-Gpx/s image capture pipeline running, it's time to rearrange some things to break the 1000fps barrier: For this clip I'm using the CMV12000's X/Y subsampling mode to trade resolution for frame rate, hitting 1440fps at…

If I were to rank the components of this project in terms of the ratio of their actual vs. expected difficulty, the NVMe interface would probably be lowest, since it was nowhere near as hard as I thought it would be.

In the original Freight Train of Pixels post, I laid out three main technical challenges to building a continuous recording 3.8Gpx/s imager.

Blue wire PCIe REFCLK still hanging in there...

I've gotten a lot of mileage out of my v0.1 (very first version) camera PCB.

I finished building up the second dual motor drive for TinyCross, which means that the electronics and wiring have finally caught up to the mechanical build and both are 100% complete!

The next stop on the Freight Train of Pixels is the wavelet compression engine.

After the second Jool launch window, I still had 196 days to get a few extra ships off Kerbin before its destruction on Year 3, Day 0.

Normally, to get the phase angle of a set of (assumed balanced) three-phase signals, I'd do a Clarke Transform followed by a atan2(β,α).

With the front wheel drive complete and the steering wheel control board working, it's finally time for a first test drive: I've been waiting over a year to see if this mountain bike air shock suspension setup would work, and it looks like it does!

In my original Freight-Train-of-Pixels post, I explored three main challenges of building a 3.8Gpx/s imager: the source, the pipe, and the sink.

Where I left off, TinyCross was at the rolling chassis stage.