Project F

Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs.

The Godbolt Compiler Explorer is a fantastic tool for assembler programmers.

This cheat sheet provides a handy guide to 32-bit RISC-V instructions.

Integer multiply and divide instructions form the optional M extension.

This RISC-V assembler post begins by examining the RISC-V jump instructions: jal and jalr.

This RISC-V assembler post covers branch and set instructions, such as beq, bltu, bgez, and slt.

This RISC-V assembler post covers load and store instructions, such as lw, sw, and lbu.

This RISC-V assembler post covers shift instructions, such as sll, srl, and srai.

This RISC-V assembler post covers bitwise logical instructions, such as and, not, and xori.

This series will help you learn and understand 32-bit RISC-V instructions and programming.

Welcome to the latest Project F news covering the first part of 2023.

Are you tired of firing up the Vivado GUI to build an FPGA project?

This FPGA demo uses fixed-point multiplication and a small framebuffer to render the Mandelbrot set.

Happy New Year and welcome to the latest Project F news covering the end of 2022.

Welcome back to my series covering mathematics and algorithms with FPGAs.

This FPGA demo effect renders four animated rasterbars.

This FPGA demo effect renders a horizontally scrolling message along a sine wave.

Welcome to Project F news for July, August, and September 2022.

In this FPGA demo, we use multiple shapes (rectangles, triangles, circles) to render a simple picture of a castle.

Project F news is back!

Sometimes you need to send a single pulse from one clock domain to another.

Welcome back to Exploring FPGA Graphics.

Welcome back to Exploring FPGA Graphics.

Welcome to your November news from Project F.

Welcome back to my series covering mathematics and algorithms with FPGAs.

Welcome to October’s update from Project F.

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in.

Welcome to my ongoing series covering mathematics and algorithms with FPGAs.

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in.

Welcome back to Exploring FPGA Graphics.

Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in.

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM.

Project F news is your monthly update on the project, with tasty tips and links thrown in.

It can be challenging to test your FPGA or ASIC graphics designs.

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month.

In this how to, we’re going to look at a straightforward method for generating sine and cosine using a lookup table.

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7.

I like to learn by doing, by trying things out and experimenting.

Welcome back to Exploring FPGA Graphics.

Welcome back to our two-part FPGA tutorial with SystemVerilog and the Digilent Nexys Video.

Welcome back to Exploring FPGA Graphics.

Hardware design can be unforgiving, so it pays to use any advantage you can get.

The square root is useful in many circumstances, including statistics, graphics, and signal processing.

In this post, I provide a quick guide to building an open-source FPGA toolchain for iCE40 boards, such as iCEBreaker, on Linux.

This two-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Nexys Video board.

Welcome back to Exploring FPGA Graphics.

Welcome back to Exploring FPGA Graphics.

In this FPGA demo we’ll experiment with Game of Life, a cellular automaton created by prolific mathematician John Conway in 1970.

Designing with FPGAs involves many types of memory, some familiar from other devices, but some that are specific to FPGAs.

Welcome back to Exploring FPGA Graphics.