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Articole: 8

  1. Machine Scheduler in LLVM - Part II

    (Min Hsu's Homepage)

    In the first part of this series, we covered the basic workflow of Machine Scheduler – LLVM’s predominated instruction scheduling framework – and learned that an instruction could go through three phases of checks before it finally got scheduled: legality…

  2. Machine Scheduler in LLVM - Part I

    (Min Hsu's Homepage)

    By this point it’s evidently that I won’t shut up talking about scheduling model in LLVM.1 I found the fact that it encodes so many low-level details pretty facinated.

  3. Calculate Throughput with LLVM's Scheduling Model

    (Min Hsu's Homepage)

    From Cambridge Dictionary: Throughput /ˈθruː.pʊt/ (noun) an amount of work done in a particular period of time.

  4. Visualize RISC-V Vector Memory Instructions

    (Min Hsu's Homepage)

    RISC-V Vector (RVV) extension has several kinds of load / store instructions which access memory in different ways.

  5. Scheduling Model in LLVM - Part II

    (Min Hsu's Homepage)

    In the previous post, we covered the basics of scheduling model in LLVM.

  6. When LLVM scalable vector meets RISC-V

    (Min Hsu's Homepage)

    There is a nice page about how LLVM handles RISC-V Vector Extension (RVV).

  7. Scheduling Model in LLVM - Part I

    (Min Hsu's Homepage)

    Instruction scheduling is essential to modern compilers.

  8. Legalizations in LLVM Backend

    (Min Hsu's Homepage)

    Ideally, compilers can build a program for a wide variety of hardware without the need to change a single line of its source code.