kate's lab notebook

If you’re just interested in the how-to – you can jump past my context.

I’ve recently been checking out a few options for inexpensive, DMM-form-factor oscilloscopes – mostly out of a desire to be able to work on hardware from anywhere with just my tiny laptop, a tiny projector, and some minimal equipment.

A common question in the #nMigen Libera.Chat channel asks how one can include a non-nMigen component—e.g. a library cell or a component from a Verilog design—so it seemed worth writing up a quick note we can link to answer that.

A common question in the #amaranth-lang Libera.Chat channel asks how one can include a non-Amaranth component—e.g. a library cell or a component from a Verilog design—so it seemed worth writing up a quick note we can link to answer that.

A few people on twitter have asked me to explain why the USB3 winds up being much harder to implement than USB2.

The MindShare book USB 3.0 Technology: Comprehensive Guide to SuperSpeed USB (ISBN-13: 978-0983646518) is a pretty decent reference for implementers of USB 3.0 / Gen1; but is published with a few factual mistakes – places where their tables incorrectly co…

I’ve written a bit about my look at “commercial off-the-shelf” USB3 PHY boards; and have been taking a look recently at the Design Gateway AB07-USBFMC module.

If you’re looking to play with commercial USB3 PHY evaluation hardware – that is, if you’re looking to get a board someone else has designed and built, rather than soldering up your own or experimenting with 5G SerDes – there seem to be two options availa…

This post is a summary of the findings from my look at using the ECP5 SerDes for USB3 LFPS for quick reference of how to use the ECP5 SerDes semi-documented out-of-band I/O features.

Lately, I’ve been developing a USB3 stack, and a USB3 frontend using the ECP5 SerDes.