Daniel Mangum

Note: all analysis and code samples used in this post correspond to the v3.3.0 release of Zephyr.

In the last two posts in the RISC-V Bytes series we have looked at a bootloader for the ESP32-C3, then built a Zephyr application that was loaded by it.

In the most recent post in the RISC-V Bytes series, we had our first experience with real hardware, exploring the bootloader on an ESP32-C3-DevKitC-02 module.

I recently acquired an ESP32-C3-DevKitC-02 module, and, as I tend to do, jumped right into reading about how the system boots and how the (pretty good!)

Upbound reached General Availability on Tuesday and today is my last day at the company.

Don’t have time to read this post?

In our most recent post in the Kubernetes API Server Adventures series we took a look at the storage interface and explored the only in-tree implementation: etcd3.

Like most API servers, a, if not the, primary function of the Kubernetes API Server is to ingest data, store it, then return it when requested.

Kubernetes is comprised of a variety of components, yet most end-user interaction with the system flows through the API Server.

Operating systems do great work, but sometimes they need a little bit of help to know when to switch from one task to another.

Twitter has been a huge part of my online community, but it has become untenable as a platform.

In our last post in the RISC-V Bytes series, I briefly alluded to the proposal to switch the Go Application Binary Interface (ABI) from a stack-based calling convention to a register-based calling convention.

If you write any code that deals with manual memory management, you are likely familiar with the concept of a “use after free” bug.

Today’s @risc_v Tip: If cross-compiling a dynamically linked program, then executing using binfmt_misc, you’ll need to both: Inform the OS where the dynamic linker resides (or invoke directly) Inform dynamic linker where other shared libraries reside (LD_…

As a relatively young person in the technology industry who is interested in low-level software and designing hardware, but spends most of my day job working on backend and distributed systems, I frequently find myself lamenting the fact that many folks in

The following is an aggregation of a Twitter thread I posted on April 14th, 2022.

I usually write about deep technical topics, frequently going into extreme detail about how systems work.

Sometimes I hear folks in the Crossplane community ask if they can just use Helm instead of opting into our package manager.

This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work.

Tonight’s @risc_v Tip: The A extension defines 2 types of instructions for atomic operations: load-reserved/store-conditional (LR/SC) and atomic fetch-and-op (AMO).

Today’s @risc_v Tip: The second PPO rule defines “Same-Address Load-Load” ordering.

Tonight’s @risc_v Tip: The first rule in RVWMO Preserved Program Order falls under the Overlapping-Address Orderings category and ensures that any loads or stores to a memory address are ordered before a subsequent store to an overlapping memory address.

Today’s @risc_v Tip: RISC-V defines its memory model (RVWMO) in the context of 3 orderings: Program Order: order of ops performed by a single hart Global Memory Order: order of ops performed by all harts Preserved Program Order: subset of program order re…

Tonight’s @risc_v Tip: The Zmmul extension species only the multiplication instructions from the M extension, allowing constrained RISC-V implementations to opt not to support division.

Today’s @risc_v Tip: Instruction-Address-Misaligned exceptions can occur when a control transfer instruction (e.g. branch / jump) provides a misaligned target.

First @risc_v Tip of 2022!

Today’s @risc_v Tip: Another new extension in the v1.12 Privileged Spec is “NAPOT Translation Continuity” (Svnapot), which allows a PTE to indicate a 64 KiB range with consistent “flags” (bits [5:0]).

Today’s @risc_v Tip: A new version of the RISC-V Privileged Architecture (v1.12) was released on Dec 3rd.

Today’s @risc_v Tip: The Zifencei extension defines one instruction, FENCE.I, which orders memory writes and instruction fetches.

Today’s @risc_v Tip: The FENCE instruction is defined as part of the base ISA and allows for explicit ordering of instructions prior to (“predecessor set”) and following (“successor set”).

This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work.

Tonight’s @risc_v Tip: Implementations may define an arbitrary number of Non-Maskable Interrupts (NMIs).

Christmas @risc_v Tip: The Zicsr extension defines instructions for clearing and setting CSR bits, which are abstracted by the pseudoinstructions csrc and csrs.

Today’s @risc_v Tip: The trap vector BASE address CSRs (mtvec / stvec) can use the lowest two bits for MODE because the BASE address must be 4-byte aligned (i.e. lowest two bits = 00).

Today’s @risc_v Tip: If using ld as your linker, a global symbol defined as start will take precedence over earlier symbols in your .text section for program entry point when explicit ENTRY is not defined in your script or via -e flag on the command line.

Today’s @risc_v Tip: Traps become more complicated in a pipelined implementation if exceptions occur after subsequent instructions have been issued.

Tonight’s @risc_vTip: Understanding marketing material for processors can be confusing.

Today’s @risc_v Tip: Regularity is a key design principle of RISC-V and has a large impact on implementation complexity.

Tonight’s @risc_v Tip: Atomicity Physical Memory Attributes (PMAs) specify support for atomic instructions described in the A extension in the Unprivileged Spec for a given range.

Tonight’s @risc_v Tip: Physical Memory Attributes (PMAs) define the capabilities of a given address range.

Today’s @risc_v Tip: The address of a Control and Status Register (CSR) encodes access and privilege level in the top 4 bits.

Today’s @risc_v Tip: Today’s tip comes courtesy of the OpenTitan (a @lowRISC project) RISC-V assembly style guide.

Tonight’s @risc_v Tip: MIT’s xv6 teaching OS is a great introduction to RISC-V.

Tonight’s @risc_v Tip: RISC-V contains a few interrupt controller specs, each providing additional functionality over basic privilege-based preemption: Core-Local Interrupt Controller (CLIC) Platform-Level Interrupt Controller (PLIC) Advanced Interrupt Ar…

Today’s @risc_v Tip: The RISC-V Hypervisor extension recently reached v1.0 and was ratified.

Tonight’s @risc_v Tip: Come join me (virtually or in person) on Monday to kick off #RISCVSummit!

Tonight’s @risc_v Tip: The Supervisor Trap Base Address CSR (stvec) indicates the location of the Supervisor (S) trap handler(s).

Tonight’s @risc_v Tip: Supervisor (S) mode has a dedicated memory-management (mm) fence instruction (SFENCE.VMA) that ensures visible stores are ordered before subsequent implicit references to mm data structures.

Tonight’s @risc_v Tip: Sv32 supports a 2-level page table, but any Page Table Entry (PTE) may be a leaf.

Tonight’s @risc_v Tip: Sv32 uses a two-level page table to enable virtual memory.