Daniel Mangum

Bonus Holiday @risc_v Tip: If the SUM bit in the sstatus CSR is 0, a PTE with U=1 means the page is not accessible from Supervisor (S) mode.

Tonight’s @risc_v Tip: A 32-bit Page Table Entry (PTE) in Sv32 virtual memory mode contains four bits that indicate access permissions.

Tonight’s @risc_v Tip: The satp CSR configures Supervisor (S) mode address translation and protection.

Today’s @risc_v Tip: Our last PMP addressing mode is Top of Range (TOR).

Tonight’s @risc_v Tip: Physical Memory Protection (PMP) and page-based virtual memory are designed to work together.

Tonight’s @risc_v Tip: Looking again at Physical Memory Protection (PMP) address matching modes, Naturally Aligned Powers of Two (NAPOT) addressing allows you to specify ranges with four-byte granularity by encoding the size in the low-order bits of the p…

Tonight’s @risc_v Tip: Yesterday we talked about the Physical Memory Protection (PMP) unit.

Tonight’s @risc_v Tip: An optional Physical Memory Protection (PMP) unit is defined that enables memory access control for software on a given hart.

Tonight’s @risc_v Tip: You might assume some exceptions, such as an ecall from User mode (U), are handled in Supervisor mode (S), but all traps are handled in Machine mode (M) by default.

Tonight’s @risc_v Tip: Continuing with the Trigger Module (TM), the RISC-V debug spec provides access to triggers via the tselect and tdata1 / tdata2 / tdata3 CSRs.

Today’s @risc_v Tip: RISC-V has a separate debug spec that defines a Debug Module (DM), Debug Module Interface (DMI), Debug Transport Module (DTM), and Trigger Module (TM).

Tonight’s @risc_v Tip: If you have ever worked with low-level programming, you may be familiar with the ambiguity of the terms exception / interrupt / trap.

Tonight’s @risc_v Tip: The GNU assembler (gas) supports a few specific RISC-V directives, including .option, which allows you to modify assembler options inline.

Tonight’s @risc_v Tip (feat.

This post references the Kubernetes codebase at commit d92a443ca7 and kube-openapi at commit ee342a809c, but should remain mostly applicable for an extended period of time barring any massive refactor to Kubernetes internals.

Tonight’s @risc_v Tip: You can use two convenient pseudo-instructions to load the address of a symbol into a CSR. la t1, main => auipc t1, main[31:12]; addi t1, t1, main[11:0] csrw mepc, t1 => csrrw x0, mepc, t1 Original Tweet

Tonight’s @risc_v Tip: You can list all the harts on the platform you are debugging with gdb using info threads.

Today’s @risc_v Tip: The mcause (M) / scause (S) CSRs indicate what type of exception caused a trap to the respective privilege level.

This post explores what a future of shipping infrastructure alongside software may look like by detailing where we are today, and evaluating how the delivery of software has evolved over time.

Today’s @risc_v Tip: The 8th bit in the Supervisor (S) Status (sstatus) CSR is called the SPP bit and indicates the hart’s privilege level before entering S mode. 0 indicates User (U) mode, and 1 indicates other.

Today’s @risc_v Tip: Machine (M) mode supports hardware performance monitoring (HPM) with the following CSRs: mcycle: number of clock cycles executed minstret: number of instructions retired mhpmcounter[3-31]: event counters mhpmevent[3-31]: event selecto…

Today’s @risc_v Tip: The satp (Supervisor Address Translation and Protection) CSR contains virtual memory translation information, including MODE.

Today’s @risc_v Tip: RISC-V systems may support 3 main privilege levels: Machine (M) (Req.)

Today’s @risc_v Tip: Fields of CSRs adhere to one of the following behaviors: WIRI: Reserved Writes Ignored, Reads Ignore Values WPRI: Reserved Writes Preserve Values, Reads Ignore Values WLRL: Write/Read Only Legal Values WARL: Write Any Values, Reads Le…

Today’s @risc_v Tip: You likely think “Hardware Security Module” when you see “HSM”.

QEMU @risc_v Tip of the Night: Running without -bios specified or with -bios default will automatically load the OpenSBI binary.

GDB tip of the day: info registers will show you the contents of general purpose registers, but info all-registers will expand the output to floating point registers and CSRs.

This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work.

I am excited to announce the launch of the Research Triangle RISC-V Community Group!

This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work.

This post is adapted from my message sent to the Kubernetes SIG Release mailing list.

This is part of a new series I am starting on the blog where we’ll explore RISC-V by breaking down real programs and explaining how they work.

This is part of a new series I am starting on the blog where we’ll explore RISC-V by breaking down real programs and explaining how they work.

For folks familiar with Crossplane, you likely know that we adopt the design practice of using interfaces over implementations as frequently as possible.

This post describes a breaking change in runc v1.0.0-rc93, that has subsequently had a workaround implemented that will presumably be included in v1.0.0-rc94.

If I was to explain LLVM in a painfully simple manner, I might say something like: “LLVM is a framework that allows you to define a syntax for interacting with computers, and instantly have it work for all computers”.

controller-runtime exposes a metrics server by default on port 8080 for any controller Manager.

If you have written a Kubernetes controller, you are likely familiar with controller-runtime, or at least client-go. controller-runtime is a framework for building controllers that allows consumers to setup multiple controllers that are all handled under a

I had the privilege of joining Steven Borrelli from Mastercard for a tutorial at Kubecon North America 2020 on building an enterprise infrastructure control plane on Kubernetes using Crossplane.

Vivado is Xilinx’s IDE for HDL synthesis and analysis.

The following is an unroll of a tweet thread about Crossplane packages that I posted after reading Dave Anderson’s post “A better Kubernetes, from the ground up”.

This post explores RISC-V assembly by examining the implementation of the setjmp and longjmp functions from the C standard library.

I joined Scott Lowe on the Full Stack Journey podcast for a chat about how Crossplane enables you to provision infrastructure from your Kubernetes cluster and allows you to compose abstractions that define your own PaaS.

If you have ever written assembly for the GNU Assembler (GAS), you may have noticed that files sometimes have an .S extension and sometimes .s.

I joined Rin Oliver on the esper.io DroidDevCast for a chat about rapid prototyping.

I joined Daniel Bryant on the Ambassador Livin’ on the Edge podcast for a chat about Crossplane, building your own PaaS, and the future of multi-cluster Kubernetes.

I had the opportunity to write up a recap and guide for the livestream I did with Alex Ellis on using Crossplane with OpenFaas.

I had the privilege of writing a guest post on the AWS Open Source Blog entitled “Connecting AWS managed services to your Argo CD pipeline with open source Crossplane”.

Jared Watts, Marques Johansson, and I sat down for a chat about Crossplane and the cloud native community with Gerhard Lazu on the Changelog Podcast at Kubecon North America 2019.

Note: While writing this post, I looked back at a post I wrote entitled Understanding ETL to ELT by Going to Costco.